1. Field of the Invention
The present invention relates to internal timing of a data write to a semiconductor memory device.
2. Description of the Related Art
In Dynamic Random Access Memory (DRAM) writing to a memory cell at an arbitrary timing as in SRAM may cause a data write error to occur.
In this type of memory device, as shown in FIG. 7, when a chip enable signal M-CE# is at an xe2x80x9cLxe2x80x9d level, when a change occurs in address signal Add, which is an external address, the memory device is actuated relative to the change. Thus, an external write signal WE# (# is indicative of being an L level and active) is activated in the latter half of a cycle of address signal Add. Relative to the change of address signal Add, address transition detection signal ATD is generated, and thereafter, in accordance with a fall of address transition detection signal ATD, row activation signal INTZPAS, word activation signal RXT, sense amplifier activation signal SO and column activation signal ZCOLRE are activated in succession.
As shown in FIG. 7, when external write signal WE# is generated in the latter half of a cycle of address signal Add, in accordance with generation of external write signal WE#, internal write signal INTWE is activated. After a predetermined time elapses from the activation, internal write control signal WDRV is activated. At the point of time when the WDRV signal is activated, column activation signal ZCOLRE is already activated. Therefore, write of data DQ is carried out according to the internal write control signal WDRV, and no related data write error occurs.
FIG. 8 illustrates a timing diagram when the external write signal WE# is activated in the first half of a cycle of address signal Add. In this case, as in the case represented by FIG. 7, relative to the change of the address signal Add, address transition detection signal ATD, row activation signal INTZPAS, word activation signal RXT, sense amplifier activation signal SO and column activation signal ZCOLRE are activated in succession.
In accordance with the generation of the external write signal WE#, internal write signal INTWE is activated. After a predetermined time elapses from this activation, internal write control signal WDRV is activated. However, because at the point of time when the WDRV signal is activated, the column activation signal ZCOLRE is not activated, the write of data DQ is not carried out according to the internal write control signal WDRV, and a related data write error occurs.
FIG. 9 illustrates a DRAM operating in a short cycle, shorter than a normal cycle. The short cycle is not conformable to the standard design. Therefore, no write is carried out. As shown, the external write signal WE# is generated for the period of the short cycle, and thereafter, a normal read cycle is carried out.
In the short cycle, internal write control signal WDRV is activated in accordance with the generation of the external write signal WE#. For this reason, when column activation signal ZCOLRE is activated (as shown by a dotted line) in the short cycle. Unnecessary, write is carried out and an error write is generated.
Usually, a design is made so that the write failure and error write are not generated. The inventor found that in the case when an internal write is carried out based on external write timing, a write failure and error write may occur depending on write timing.
An object of the present invention is to provide a memory device, which can carry out a normal write in a normal cycle without generating error write in various write timings.
In DRAM, data write is carried out when a column activation signal ZCOLRE is activated with a change of an internal address Add and an internal write control signal WDRV is activated by a generation of an external write signal WE. However, when the data write is carried out at an arbitrary timing, no data write is carried out in some cases.
In order to solve the above problem, according to an aspect of the disclosed concepts, a semiconductor memory device includes a delay circuit for delaying an output of the internal write control signal WDRV until the column activation signal ZCOLRE is activated even if the write signal WE is generated.
Moreover, in the case where the external write signal WE# is generated under a short cycle, when the column activation signal ZCOLRE is activated in the prior cycle, a problem arises such that error write is generated.
In order to solve the above problem, according to another aspect of the disclosed concepts, a semiconductor memory device includes a non-activation circuit for prohibiting activation of the internal write control signal WDRV by a change of the address signal of the next cycle when the external write signal WE# is inputted under a short cycle in which the external address signal is inputted in a short period shorter than a predetermined period.